Inline power controller

ABSTRACT

An inline power controller includes at least one analog interface circuit module (AICM) having a first analog input node for receiving an inline power port voltage, a second analog input node for receiving an inline power port current, a first analog output for effecting an inline power port voltage, a second analog output for effecting an inline power port current, and a digital interface converting the received inline power port voltage to a digital value, the inline power port current to a digital value, a first digital value to the first analog output and a second digital value to the second analog output. A digital serial bus (DSB) couples the AICM to a digital controller via digital serial bus interfaces (DSBIs).

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of co-pending U.S. patent applicationSer. No. 11/191,629, filed on Jul. 27, 2005, entitled “Inline PowerController” in the name of the same inventors and commonly ownedherewith.

FIELD OF THE INVENTION

The present invention relates generally to networking equipment which ispowered by and/or powers other networking equipment over wired datatelecommunications network connections.

BACKGROUND OF THE INVENTION

Inline power (also known as Power over Ethernet and PoE) is a technologyfor providing electrical power over a wired telecommunications networkfrom power source equipment (PSE) to a powered device (PD) over a linksection. The power may be injected by an endpoint PSE at one end of thelink section or by a midspan PSE along a midspan of a link section thatis distinctly separate from and between the medium dependent interfaces(MDIs) to which the ends of the link section are electrically andphysically coupled.

PoE is defined in the IEEE (The Institute of Electrical and ElectronicsEngineers, Inc.) Standard Std 802.3af-2003 published 18 Jun. 2003 andentitled “IEEE Standard for Information technology—Telecommunicationsand information exchange between systems—Local and metropolitan areanetworks—Specific requirements: Part 3 Carrier Sense Multiple Accesswith Collision Detection (CSMA/CD) Access Method and Physical LayerSpecifications: Amendment: Data Terminal Equipment (DTE) Power via MediaDependent Interface (MDI)” (herein referred to as the “IEEE 802.3afstandard”). The IEEE 820.3af standard is a globally applicable standardfor combining the transmission of Ethernet packets with the transmissionof DC-based power over the same set of wires in a single Ethernet cable.It is contemplated that Inline power will power such PDs as InternetProtocol (IP) telephones, surveillance cameras, switching and hubequipment for the telecommunications network, biomedical sensorequipment used for identification purposes, other biomedical equipment,radio frequency identification (RFID) card and tag readers, securitycard readers, various types of sensors and data acquisition equipment,fire and life-safety equipment in buildings, and the like. The power isdirect current, 48 Volt power available at a range of power levels fromroughly 0.5 watt to about 15.4 watts in accordance with the standard.Higher power levels are anticipated for the future. There are mechanismswithin the IEEE 802.3af standard to allocate a requested amount ofpower. Other proprietary schemes also exist to provide a finer and moresophisticated allocation of power than that provided by the IEEE 802.3afstandard while still providing basic compliance with the standard. Asthe standard evolves, additional power may also become available.Conventional 8-conductor type RG-45 connectors (male or female, asappropriate) are typically used on both ends of all Ethernetconnections. They are wired as defined in the IEEE 802.3af standard. Twoconductor wiring such as shielded or unshielded twisted pair wiring (orcoaxial cable or other conventional network cabling) may be used so eachtransmitter and receiver has a pair of conductors associated with it.

FIGS. 1A, 1B and 1C are electrical schematic diagrams of three differentvariants of PoE as contemplated by the IEEE 802.3af standard. In FIG. 1Aa data telecommunications network 10 a comprises a switch or hub 12 awith integral power sourcing equipment (PSE) 14 a. Power from the PSE 14a is injected on the two data carrying Ethernet twisted pairs 16 aa and16 ab via center-tapped transformers 18 aa and 18 ab. Non-data carryingEthernet twisted pairs 16 ac and 16 ad are unused in this variant. Thepower from data carrying Ethernet twisted pairs 16 aa and 16 ab isconducted from center-tapped transformers 20 aa and 20 ab to powereddevice (PD) 22 a for use thereby as shown. In FIG. 1B a datatelecommunications network 10 b comprises a switch or hub 12 b withintegral power sourcing equipment (PSE) 14 b. Power from the PSE 14 b isinjected on the two non-data carrying Ethernet twisted pairs 16 bc and16 bd. Data carrying Ethernet twisted pairs 16 ba and 16 bb are unusedin this variant for power transfer. The power from non-data carryingEthernet twisted pairs 16 bc and 16 bd is conducted to powered device(PD) 22 b for use thereby as shown. In FIG. 1C a data telecommunicationsnetwork 10 c comprises a switch or hub 12 c without integral powersourcing equipment (PSE). Midspan power insertion equipment 24 simplypasses the data signals on the two data carrying Ethernet twisted pairs16 ca-1 and 16 cb-1 to corresponding data carrying Ethernet twistedpairs 16 ca-2 and 16 cb-2. Power from the PSE 14 c located in theMidspan power insertion equipment 24 is injected on the two non-datacarrying Ethernet twisted pairs 16 cc-2 and 16 ed-2 as shown. The powerfrom non-data carrying Ethernet twisted pairs 16 cc-2 and 16 cd-2 isconducted to powered device (PD) 22 c for use thereby as shown. Notethat powered end stations 26 a, 26 b and 26 c are all the same so thatthey can achieve compatibility with each of the previously describedvariants.

Turning now to FIGS. 1D and 1E, electrical schematic diagrams illustratevariants of the IEEE 802.3af standard in which 1000 Base Tcommuunication is enabled over a four pair Ethernet cable. Inline powermay be supplied over two pairs or four pairs of conductors although thepresent IEEE 802.3af standard only provides for power over two pairs. InFIG. 1D the PD accepts power from a pair of diode bridge circuits suchas full wave diode bridge rectifier type circuits well known to those ofordinary skill in the art. Power may come from either one or both of thediode bridge circuits, depending upon whether inline power is deliveredover Pair 1-2, Pair 3-4 or Pair 1-2+Pair 3-4. In the circuit shown inFIG. 1E a PD associated with Pair 1-2 is powered by inline power overPair 1-2 and a PD associated with Pair 3-4 is similarly powered. Theapproach used will depend upon the PD to be powered. In accordance withboth of these versions, bidirectional full duplex communication may becarried out over each data pair, if desired.

Inline power is also available through techniques that are non-IEEE802.3 standard compliant as is well known to those of ordinary skill inthe art.

In order to provide regular inline power to a PD from a PSE it is ageneral requirement that two processes first be accomplished. First, a“discovery” process must be accomplished to verify that the candidate PDis, in fact, adapted to receive inline power. Second, a “classification”process must be accomplished to determine an amount of inline power toallocate to the PD, the PSE having a finite amount of inline powerresources available for allocation to coupled PDs.

The discovery process looks for an “identity network” at the PD. Theidentity network is one or more electrical components which respond incertain predetermined ways when probed by a signal from the PSE. One ofthe simplest identity networks is a resistor coupled across the twopairs of common mode power/data conductors. The IEEE 802.3af standardpermits a 25,000 ohm resistor to be presented for discovery by the PDbecause it is within the permissible range of values (other values maybe used instead in accordance with the standard). The resistor may bepresent at all times or it may be switched into the circuit during thediscovery process in response to discovery signals from the PSE.

The PSE applies some inline power (not “regular” inline power, i.e.,reduced voltage and limited current) as the discovery signal to measureresistance across the two pairs of conductors to determine if the 25,000ohm identity network is present. This is typically implemented as afirst voltage for a first period of time and a second voltage for asecond period of time, both voltages exceeding a maximum idle voltage(0-5 VDC in accordance with the IEEE 802.3af standard) which may bepresent on the pair of conductors during an “idle” time while regularinline power is not provided. The discovery signals do not enter aclassification voltage range (typically about 15-20V in accordance withthe IEEE 802.3af standard) but have a voltage between that range and theidle voltage range. The return currents responsive to application of thediscovery signals are measured and a resistance across the two pairs ofconductors is calculated. If that resistance is the identity networkresistance, then the classification process may commence, otherwise thesystem returns to an idle condition.

In accordance with the IEEE 802.3af standard, the classification processinvolves applying a voltage in a classification range to the PD. The PDmay use a current source to send a predetermined classification currentsignal back to the PSE. This classification current signal correspondsto the “class” of the PD. In the IEEE 802.3af standard as presentlyconstituted, the classes are as set forth in Table I:

TABLE I PSE Classification Corresponding Class Current Range (mA) InlinePower Level (W) 0 0-5 15.4 1  8-13 4.0 2 16-21 7.0 3 25-31 15.4 4 35-45Reserved

The discovery process is therefore used in order to avoid providinginline power (at full voltage of −48 VDC) to so-called “legacy” deviceswhich are not particularly adapted to receive or utilize inline power.

The classification process is therefore used in order to manage inlinepower resources so that available power resources can be efficientlyallocated and utilized.

In wired data telecommunications networks it would be advantageous toprovide improved means for efficiently handling inline power discovery,classification and provision and protection.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated into and constitute apart of this specification, illustrate one or more embodiments of thepresent invention and, together with the detailed description, serve toexplain the principles and implementations of the invention.

In the drawings:

FIGS. 1A, 1B, 1C, 1D and 1E are electrical schematic diagrams ofportions of data telecommunications networks in accordance with theprior art.

FIG. 2 is a system block diagram of a system including a network deviceCPU (central processing unit) and a plurality of coupled inline powercontroller circuits in accordance with one embodiment of the presentinvention.

FIG. 3 is a system block diagram of an analog interface circuit moduleand its digital interface circuitry in accordance with one embodiment ofthe present invention.

FIG. 4A is an electrical schematic diagram illustrating theconfiguration of a PSE and a PD in accordance with the present inventionduring the inline power discover phase.

FIG. 4B is an electrical schematic diagram illustrating theconfiguration of a PSE and a PD in accordance with the present inventionduring the inline power classification phase.

FIG. 4C is an electrical schematic diagram illustrating theconfiguration of a PSE and a PD in accordance with the present inventionduring the inline power powered device powering phase.

FIG. 5 is a process flow diagram illustrating a method for controllinginline power port current and voltage in accordance with one embodimentof the present invention.

DETAILED DESCRIPTION

Embodiments of the present invention described in the following detaileddescription are directed at inline power controllers. Those of ordinaryskill in the art will realize that the detailed description isillustrative only and is not intended to restrict the scope of theclaimed inventions in any way. Other embodiments of the presentinvention, beyond those embodiments described in the detaileddescription, will readily suggest themselves to those of ordinary skillin the art having the benefit of this disclosure. Reference will now bemade in detail to implementations of the present invention asillustrated in the accompanying drawings. Where appropriate, the samereference indicators will be used throughout the drawings and thefollowing detailed description to refer to the same or similar parts.

In the interest of clarity, not all of the routine features of theimplementations described herein are shown and described. It will, ofcourse, be appreciated that in the development of any such actualimplementation, numerous implementation-specific decisions must be madein order to achieve the developer's specific goals, such as compliancewith application- and business-related constraints, and that thesespecific goals will vary from one implementation to another and from onedeveloper to another. Moreover, it will be appreciated that such adevelopment effort might be complex and time-consuming, but wouldnevertheless be a routine undertaking of engineering for those ofordinary skill in the art having the benefit of this disclosure.

FIG. 2 is a system block diagram of a system including a network deviceCPU (central processing unit) and a plurality of coupled inline powercontroller circuits in accordance with one embodiment of the presentinvention.

FIG. 2 illustrates a system for inline powered port control as might befound in a typical network device such as a switch, router or the like.In the embodiment 200 illustrated in FIG. 2, a network device CPU(central processing unit) 202 operating under the control of anoperating system such as CISCO IOS® available from Cisco Systems, Inc.of San Jose, Calif., is coupled to one or more inline power controllermodules 204 a, 204 b, . . . , 204 n through a first communications bus206 as shown. The CPU handles high-level communications between thenetwork device and the respective inline power controller modules 204 a,204 b, . . . , 204 n as is known to those of ordinary skill in the art.

Inline power controller module 204 a, for example, includes a digitalcontroller 208 and a program memory 210 in which are stored instructionsunder which digital controller 208 operates. In one embodiment these maybe updated from time to time via communications with CPU 202 by havingCPU 202 download new instructions and storing them in program memory210. Digital controller 208 communicates with one or more port analoginterface circuit modules (AICMs) 212 a, 212 b, . . . , 212 m over aloop-configured digital serial bus interface (DSB) 214 as shown. DSB 214is implemented in one embodiment of the present invention as a singlebit wide serial bus with each AICM 212 a, 212 b, . . . , 212 m having aregister of the same width and length so that digital signals to betransmitted to the various AICMs may be easily clocked out to them overthe DSB and digital signals to be received from them may similarly beclocked back to the digital controller 208. It is also possible to usemore than one bit of width in the DSB, depending upon the speed of thedevices used, the amount of data to be conveyed, and the refresh raterequired by the particular application. A digital serial bus interface(DSBI) is provided at each device that needs to interface with the DSB214.

AICM 212 a includes a digital component 216, an analog component 218 andone or more inline-powered ports for providing inline powered datatelecommunications in a wired data telecommunications network.

FIG. 3 is a system block diagram of an analog interface circuit module(AICM) 212 a and its digital interface circuitry 216 in accordance withone embodiment of the present invention.

The AICM 212 a includes analog component 218 which receivesanalog-valued signals representing inline power port voltage and currentfrom one or more attached inline powered ports 220. One module 212 a canservice one or more inline powered ports 220 by cycling among them ineither a time-sliced manner, a demand-based manner, or a combination ofthe two. AICM 212 a also sends analog-valued voltage and currenteffector signals to the inline powered port circuitry to cause thatcircuitry to adjust its voltage and/or current in response to commandsfrom the digital controller 208. The analog signals are converted todigital in digital interface 222 where conventional analog to digitalconverters (ADCs) convert the inline power port voltage and currentsignals to digital-valued signals which can then be transmitted to thedigital controller 208. Similarly, the digital interface 222 alsoincludes digital to analog converters (DACs) for converting the digitalvoltage and current effector signals from the digital controller 208 tocorresponding analog-valued signals for application to the inlinepowered port circuitry 220. Such central resources as ADCs and DACs maybe shared, if desired, using a conventional multiplexer circuit, as iswell known to those of ordinary skill in the art.

Note that the analog voltage and current values may be measured in anysuitable manner using conventional techniques available to those ofordinary skill in the art for measuring current and voltage.

The digital interface circuitry 216 also includes DSB interfacecircuitry 224 which buffers and controls the aforementioned digitalsignals for communication with the DSBI register 226 which forms part ofthe DSB 214 as discussed above.

Digital communications occur as follows: a digital signal generated atthe digital controller 208 is transmitted onto the DSB 214 at a DSBIoutput 230 of the digital controller 208 in the form of a digital signalof width W (in bits) and length L (in bits). What is needed is to shiftthe contents of the AICM registers into the digital controller 208 overthe DSB 214 and to shift new data and/or instructions from the digitalcontroller 208 over the DSB 214 to the respective AICM registers. If them AICM registers are thought of as one big shift register, then it has alength of m*L bits and a width of W bits. Thus, the last L bits of thesignal are shifted by this operation to the first AICM 212 a, the nextto last L bits of the signal are shifted to the second AICM 212 b, andso on. Bits are shifted from the AICM registers back into a DSBI input232 of digital controller 208. Each DSBI register 226 at eachcorresponding AICM (e.g., AICM 212 a) has a DSBI input 234 and a DSBIoutput 236.

FIG. 4A is an electrical schematic diagram illustrating a configuration400 of a PSE and a PD in accordance with the present invention duringthe inline power discovery phase. FIG. 4B is an electrical schematicdiagram illustrating a configuration 402 of a PSE and a PD in accordancewith the present invention during the inline power classification phase.FIG. 4C is an electrical schematic diagram illustrating a configuration404 of a PSE and a PD in accordance with the present invention duringthe inline power powered device powering phase.

In configuration 400 an ADC 406 is coupled in parallel with a currentsource 408 at PSE 410. The PSE 410 is coupled as discussed above over awired data telecommunications network such as Ethernet through MediaDependent Interfaces (MDIs) to PD 412 which includes a fill wave bridgerectifier 414 (other forms of rectification could be used) and anidentity network 416 such as a 25 k ohm resistor.

Discovery or detection is accomplished in one embodiment of theinvention by stimulating the current source 408 (possibly with a DAC—notshown) to produce a first current i(1) and measuring a responsivevoltage v(1) across nodes 418 (418 a and 418 b) with ADC 406. Then thecurrent source 408 is stimulated to produce a second current i(2) and asecond responsive voltage v(2) is measured across nodes 418. Aresistance is then calculated using the formulaR=(i(2)−i(1))/(v(2)−v(1)). If the resistance is within the acceptablerange, then the classification phase is entered. If not, classificationdoes not occur. The current source 408 in this case is implemented witha fixed current source to generate i(1) or i(2). It could, however, beimplemented as a current output DAC which can output i(1) or i(2). Othermethods of discovery may be used without departing from the essence ofthe present invention.

In configuration 402 (classification phase) a power source 420 (whichmay be implemented as a fixed voltage source as shown or, alternatively,as a voltage output DAC) provides a voltage to the PSE circuit 421.R(sense) is a sense resistor. An ADC 422 coupled in parallel withR(sense) is used to measure current i(class). Current i(class) isdetermined by the nature of the current sink 424 of the PD. The measuredi(class) is used to classify the PD and set the maximum power (current)level to be provided to the PD 426 from the PSE 421. Note that a numberof other means may be used to determine i(class).

In configuration 404 (powering phase) a power source 428 provides powerat the PSE 430 for powering the PD 432. R(sense) is coupled as inconfiguration 402 to allow ADC-1 to measure port current (i(port)).Hardware (HW) is used to constantly monitor the current across R(sense)for a catastrophic over current condition. In such a condition, thecircuit will be depowered to avoid damage. ADC-2 measures the portvoltage v(port) across power source 428 at the port. Thus conventionalhardware circuitry (HW) is used for critical instantaneous currentmeasurements while the ADC-1 is used to measure current periodically foruse by the software/firmware routines in the digital controller 208.Note that in this configuration 404, it is unlikely (but possible) thatpower source 428 would be implemented as a DAC because a reasonableamount of current will need to be supplied in the powering phase ofoperation thus making a different sort of power supply more practical inthis application.

In the PD 432 a conventional DC/DC (direct current to direct current)converter 434 provides inline power to R(load) 436 in a conventionalmanner.

FIG. 5 is a process flow diagram 500 illustrating a method forcontrolling inline power port current and voltage in accordance with oneembodiment of the present invention.

Six steps are illustrated in FIG. 5. These are:

Step 502: Transmitting digital current effector or digital voltageeffector signals from a digital controller over a digital serial bus toan analog interface circuit module;

Step 504: Converting the received digital current effector or digitalvoltage effector signals to corresponding analog signals at the analoginterface circuit module;

Step 506: Applying the analog current effector or analog voltageeffector signals to an inline power port coupled to the analog interfacecircuit module;

Step 508: Receiving analog current or analog voltage signals at theanalog interface circuit module from the inline power port;

Step 510: Converting the received analog current or analog voltagesignals to corresponding digital signals at the analog interface circuitmodule; and

Step 512: Transmitting the digital current or digital voltage signalsfrom the analog interface circuit module over the digital serial bus tothe digital controller.

In accordance with the described method, the operation of the inlinepower ports is effected to carry out inline power discovery,classification, operation and protection steps in accordance with, forexample, the IEEE 802.3af standard, or other standards or proprietarysystems to be implemented.

Using the DSB approach described herein, it is also possible to extendthe instruction word length (L) used in the digital interface circuitry216 in the future without any need to completely rewrite the underlyingprogram instructions. This is achieved as follows. Say, for example,that the present word length L is 8 bits and in the future it is desiredto develop a more complex system that requires 16 bits of word length.Instead of shifting L multiplied by the number of AICMs in the systemthrough the DSB, we shift L′ (the new value of L) multiplied by thenumber of AICMs in the system. For “old” instructions, a null operationcode “NULL” is sent as the bits corresponding to the “extra” bits. Thusif the “old” instruction was: [DDDD DDDD] the new instruction would be[xxxx xxxx DDDD DDDD] or [DDDD DDDD xxxx xxxx] where “xxxx xxxx” is thecode for the NULL. The digital controller 208 can easily be programmedto carry out this function as can some future digital controller. Aswill now be apparent to those of ordinary skill in the art having thebenefit of this disclosure, the word length can be extended essentiallyindefinitely using this approach and this approach has application toother sorts of digital serial bus implementations beyond the field ofnetwork devices.

While embodiments and applications of this invention have been shown anddescribed, it will now be apparent to those skilled in the art havingthe benefit of this disclosure that many more modifications thanmentioned above are possible without departing from the inventiveconcepts disclosed herein. Therefore, the appended claims are intendedto encompass within their scope all such modifications as are within thetrue spirit and scope of this invention.

1. An inline power controller, comprising: at least one analog interfacecircuit module, the analog interface circuit module having: a firstanalog input node for receiving an inline power port voltage; a secondanalog input node for receiving an inline power port current; a firstanalog output for effecting an inline power port voltage; a secondanalog output for effecting an inline power port current; a digitalinterface configured to convert the received inline power port voltageto a first digital value, the inline power port current to a seconddigital value, a third digital value to the first analog output and afourth digital value to the second analog output; and a digital serialbus (DSB); and a digital controller responsive to a series ofinstructions stored in a programmable memory associated with the digitalcontroller; the digital controller coupled to communicate with the atleast one analog interface circuit module via the DSB; and the digitalcontroller configured to carry out inline power operation and protectionsteps.
 2. The inline power controller of claim 1, wherein the DSB has awidth of more than one bit.
 3. The inline power controller of claim 1,wherein the digital controller is further configured to carry out inlinepower discovery.
 4. The inline power controller of claim 1, wherein thedigital controller is further configured to carry out inline powerclassification.
 5. An inline power controller, comprising: at least oneanalog interface circuit, the analog interface circuit having: a firstinput for receiving an inline power port voltage; a second input forreceiving an inline power port current; a first output for effecting aninline power port voltage; a second output for effecting an inline powerport current; a digital interface configured to convert the receivedinline power port voltage to a first digital value, the inline powerport current to a second digital value, a third digital value to thefirst output and a fourth digital value to the second output; a digitalserial bus (DSB); and a digital controller responsive to instructionsstored in a program memory associated with the digital controller andcoupled to communicate with the at least one analog interface circuitvia the DSB.
 6. The inline power controller of claim 5, wherein the DSBhas a width of more than one bit.
 7. The inline power controller ofclaim 5, wherein the digital controller is further configured to carryout inline power discovery.
 8. The inline power controller of claim 5,wherein the digital controller is further configured to carry out inlinepower classification.
 9. The inline power controller of claim 5, whereinthe digital controller is further configured to carry out inline poweroperation and protection steps.
 10. An inline power controller,comprising: at least one interface circuit, the interface circuithaving: a first input for receiving an inline power port voltage; asecond input for receiving an inline power port current; a first outputconfigured to transmit voltage effector signals; a second outputconfigured to transmit current effector signals; a digital interfaceconfigured to convert the received inline power port voltage to a firstdigital value, the inline power port current to a second digital value,a third digital value to the first output and a fourth digital value tothe second output; a digital serial bus (DSB); and a digital controllerresponsive to instructions stored in a program memory associated withthe digital controller and coupled to communicate with the at least oneinterface circuit via the DSB.
 11. The inline power controller of claim10, wherein the DSB has a width of more than one bit.
 12. The inlinepower controller of claim 10, wherein the digital controller is furtherconfigured to carry out inline power discovery.
 13. The inline powercontroller of claim 10, wherein the digital controller is furtherconfigured to carry out inline power classification.
 14. The inlinepower controller of claim 10, wherein the digital controller is furtherconfigured to carry out inline power operation and protection steps.